arXiv:2511.21232v1 Announce Type: cross 
Abstract: The increasing demand for on-device intelligence in Edge AI and TinyML applications requires the efficient execution of modern Convolutional Neural Networks (CNNs). While lightweight architectures like MobileNetV2 employ Depthwise Separable Convolutions (DSC) to reduce computational complexity, their multi-stage design introduces a critical performance bottleneck inherent to layer-by-layer execution: the high energy and latency cost of transferring intermediate feature maps to either large on-chip buffers or off-chip DRAM. To address this memory wall, this paper introduces a novel hardware accelerator architecture that utilizes a fused pixel-wise dataflow. Implemented as a Custom Function Unit (CFU) for a RISC-V processor, our architecture eliminates the need for intermediate buffers entirely, reducing the data movement up to 87\% compared to conventional layer-by-layer execution. It computes a single output pixel to completion across all DSC stages-expansion, depthwise convolution, and projection-by streaming data through a tightly-coupled pipeline without writing to memory. Evaluated on a Xilinx Artix-7 FPGA, our design achieves a speedup of up to 59.3x over the baseline software execution on the RISC-V core. Furthermore, ASIC synthesis projects a compact 0.284 mm$^2$ footprint with 910 mW power at 2 GHz in 28 nm, and a 1.20 mm$^2$ footprint with 233 mW power at 300 MHz in 40 nm. This work confirms the feasibility of a zero-buffer dataflow within a TinyML resource envelope, offering a novel and effective strategy for overcoming the memory wall in edge AI accelerators.

تم تقديم بنية جديدة لمسرع الأجهزة تستخدم تدفق بيانات بكسل مدمج لعمليات الالتفاف القابلة للفصل في العمق (DSC) في تطبيقات الذكاء الاصطناعي على الحافة. تم تنفيذ هذه البنية كوحدة وظيفة مخصصة (CFU) لمعالج RISC-V، مما يقلل بشكل كبير من حركة البيانات بنسبة تصل إلى 87% مقارنة بأساليب التنفيذ التقليدية طبقة تلو الأخرى.

Se ha introducido una nueva arquitectura de acelerador de hardware que utiliza un flujo de datos pixel por pixel fusionado para las convoluciones separables en profundidad (DSC) en aplicaciones de Edge AI. Esta arquitectura, implementada como una Unidad de Función Personalizada (CFU) para un procesador RISC-V, reduce significativamente el movimiento de datos hasta en un 87 % en comparación con los métodos de ejecución tradicionales capa por capa.

Une nouvelle architecture d'accélérateur matériel a été introduite, utilisant un flux de données pixel par pixel fusionné pour les convolutions séparables en profondeur (DSC) dans les applications d'Edge AI. Cette architecture, mise en œuvre en tant qu'unité fonctionnelle personnalisée (CFU) pour un processeur RISC-V, réduit considérablement le mouvement des données jusqu'à 87 % par rapport aux méthodes d'exécution traditionnelles couche par couche.

A novel hardware accelerator architecture has been introduced that utilizes a fused pixel-wise dataflow for Depthwise Separable Convolutions (DSC) in Edge AI applications. This architecture, implemented as a Custom Function Unit (CFU) for a RISC-V processor, significantly reduces data movement by up to 87% compared to traditional layer-by-layer execution methods.

RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI

arXiv:2512.08198v1 Announce Type: new 
Abstract: Camera-based animal re-identification (Animal Re-ID) can support wildlife monitoring and precision livestock management in large outdoor environments with limited wireless connectivity. In these settings, inference must run directly on collar tags or low-power edge nodes built around microcontrollers (MCUs), yet most Animal Re-ID models are designed for workstations or servers and are too large for devices with small memory and low-resolution inputs. We propose an on-device framework. First, we characterise the gap between state-of-the-art Animal Re-ID models and MCU-class hardware, showing that straightforward knowledge distillation from large teachers offers limited benefit once memory and input resolution are constrained. Second, guided by this analysis, we design a high-accuracy Animal Re-ID architecture by systematically scaling a CNN-based MobileNetV2 backbone for low-resolution inputs. Third, we evaluate the framework with a real-world dataset and introduce a data-efficient fine-tuning strategy to enable fast adaptation with just three images per animal identity at a new site. Across six public Animal Re-ID datasets, our compact model achieves competitive retrieval accuracy while reducing model size by over two orders of magnitude. On a self-collected cattle dataset, the deployed model performs fully on-device inference with only a small accuracy drop and unchanged Top-1 accuracy relative to its cluster version. We demonstrate that practical, adaptable Animal Re-ID is achievable on MCU-class devices, paving the way for scalable deployment in real field environments.

تم اقتراح إطار عمل جديد لإعادة تحديد الهوية الحيوانية المعتمد على الكاميرات (Animal Re-ID)، مما يتيح مراقبة الحياة البرية وإدارة الماشية بدقة على وحدات التحكم الدقيقة (MCUs) في بيئات ذات اتصال محدود. يتناول هذا الإطار التحديات المتعلقة بتشغيل نماذج معقدة على أجهزة منخفضة الطاقة من خلال تصميم بنية عالية الدقة تعتمد على هيكل MobileNetV2 الموسع لإدخالات منخفضة الدقة.

Se ha propuesto un nuevo marco para la re-identificación animal basada en cámaras (Animal Re-ID), que permite la monitorización de la vida silvestre y la gestión precisa del ganado en microcontroladores (MCUs) en entornos con conectividad limitada. Este marco aborda los desafíos de ejecutar modelos complejos en dispositivos de bajo consumo al diseñar una arquitectura de alta precisión basada en un backbone MobileNetV2 escalado para entradas de baja resolución.

Un nouveau cadre pour la ré-identification animale basée sur des caméras (Animal Re-ID) a été proposé, permettant la surveillance de la faune et la gestion précise du bétail sur des microcontrôleurs (MCUs) dans des environnements avec une connectivité limitée. Ce cadre répond aux défis de l'exécution de modèles complexes sur des dispositifs à faible consommation d'énergie en concevant une architecture de haute précision basée sur un backbone MobileNetV2 mis à l'échelle pour des entrées à basse résolution.

A new framework for camera-based animal re-identification (Animal Re-ID) has been proposed, enabling wildlife monitoring and precision livestock management on microcontrollers (MCUs) in environments with limited connectivity. This framework addresses the challenges of running complex models on low-power devices by designing a high-accuracy architecture based on a scaled MobileNetV2 backbone for low-resolution inputs.

Animal Re-Identification on Microcontrollers

As intelligence moves from data centres to devices, edge AI promises speed, autonomy and privacy, but exposes a web of security challenges.

تتقدم الذكاء الاصطناعي على الحافة بسرعة مع انتقال الذكاء من مراكز البيانات المركزية إلى الأجهزة اللامركزية، مما يوفر فوائد مثل زيادة السرعة، والاستقلالية، وتحسين الخصوصية. ومع ذلك، فإن هذا التحول يقدم أيضًا مجموعة معقدة من التحديات الأمنية التي يجب معالجتها لضمان نشر آمن.

La IA de borde avanza rápidamente a medida que la inteligencia se traslada de los centros de datos centralizados a los dispositivos descentralizados, ofreciendo beneficios como mayor velocidad, autonomía y privacidad mejorada. Sin embargo, este cambio también introduce una compleja variedad de desafíos de seguridad que deben abordarse para garantizar un despliegue seguro.

L'IA de périphérie progresse rapidement alors que l'intelligence passe des centres de données centralisés aux dispositifs décentralisés, offrant des avantages tels qu'une vitesse accrue, une autonomie et une meilleure confidentialité. Cependant, ce changement introduit également un ensemble complexe de défis en matière de sécurité qui doivent être résolus pour garantir un déploiement sûr.

Edge AI is rapidly advancing as intelligence transitions from centralized data centers to decentralized devices, offering benefits such as increased speed, autonomy, and enhanced privacy. However, this shift also introduces a complex array of security challenges that must be addressed to ensure safe deployment.

RISC-V Based TinyML Accelerator for Depthwise Separable Convolutions in Edge AI

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