The paper presents QiMeng-SALV, a novel approach designed to improve Verilog code generation by leveraging Signal-Aware Learning. This method specifically targets the enhancement of Large Language Models’ ability to produce functionally correct Verilog code, addressing a key challenge in preference optimization caused by the absence of meaningful functional rewards. By incorporating signal-awareness into the learning process, QiMeng-SALV aims to guide the model more effectively toward generating accurate hardware description language code. The approach is proposed as a solution to overcome limitations in existing methods that struggle with functional correctness in code generation tasks. Initial claims suggest that QiMeng-SALV positively impacts the effectiveness of Verilog code synthesis, although detailed empirical results are not provided in the summary. This development aligns with ongoing efforts to refine AI-driven code generation by integrating domain-specific knowledge to improve output quality. The introduction of QiMeng-SALV marks a step forward in addressing the complexities of hardware design automation through advanced machine learning techniques.